1. Field of the Invention
The present invention relates to a network control method of calculating the in time interrupt point by means of the application of a fuzzy theory, and relates more particularly to such a network control method which employs a fuzzy theory to calculate the time point of producing the interrupt signal, so as to produce the interrupt signal in time before the data of the packet is completely stored in the buffer memory (or the data buffer of the host system). This method greatly shortens the time delay in processing the data of the packet, and improves the data processing speed of the network system. The invention relates also to the apparatus for the application of the network control method.
2. Description of the Prior Art
In the frame structure of an ethernet packet, as shown in FIG. 1, the first 8-byte set are the preamble and the start frame delimiter (SFD), the next 12-byte set are the destination and the source address, the further next 2-byte is the length , and the last are the data portion and the CRC (cyclic redundancy check). In a regular network as shown in FIG. 2, the network card 11 is comprised of a network controller 112, and a transceiver 111. The packet is transmitted from the transmission line 10 to the transceiver 111 of the network card 11, and then sent from the transceiver 111 to the network controller 112 after having been converted to a suitable form by the transceiver 111. The network controller 112 comprises a network interface logic 113, an interrupt threshold control logic 114, a buffer memory 115, and a host system interface logic 116. The interrupt threshold control logic 114 of the network controller 112 checks the packet being transmitted from the transceiver 111 whether the destination address of the packet is in conformity with its destination address. If the destination address of the packet is not in conformity with that of the interrupt threshold control logic 114 of the network controller 112, the network controller 112 stops processing the data. If the destination address of the packet is in conformity with that of the interrupt threshold control logic 114 of the network controller 112, the network controller 112 immediately stores the data of the packet in the buffer memory 115 (or the data buffer 122 of the host system 12) through the network interface logic 113. After the data of the packet has been completely stored in the buffer memory 115 (or the data buffer 122 of the host system 12), the interrupt threshold control logic 114 immediately checks the FCS(frame check sequence) of the packet. If the FCS is checked accurate, it means a normal packet has been received, thus, the interrupt threshold control logic 114 immediately sends an interrupt signal to the CPU 123 through the host system interface logic 116, informing the CPU 123 to process the data. According to the operation of this network system, as shown in FIG. 3, there is a time delay At after the presence of the interrupt signal before the processing of the data of the packet by the CPU. Furthermore, because the software takes a lot of time in processing the data, a certain length of time delay exists before the host system finishes the process of the data and after the production of the interrupt signal from the network controller 112. Because of this time delay, the bandwidth of the network system cannot be fully utilized, thereby causing the data transmission efficiency of the network system cannot be greatly improved.